eroflex circuit technology - advanced multichip modules ? scd1661b rev a 1/16/97 general description utilizing intel?s smartvoltage boot block flash memory smartdie?, the act?f1m32 is a high speed, 32 megabit cmos flash multichip module (mcm) designed for full temperature range military, space, or high reliability applications. the act-f1m32 consists of four high-performance intel x28f800bv 8 mbit (8,388,608 bit) memory die. each die contains separately erasable blocks, including a hardware lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each), and 8 main blocks (one block of 98,304 bytes and seven blocks of 131,072 bytes) this defines the boot block flash family architecture. the command register is written by bringing we to a logic low level (v i l ), while ce is low and oe is high (v i h ) . reading is features block diagram ? cqfp(f14) block diagram ? cqfp(f14) n 4 low voltage/power intel 1m x 8 flash die in one mcm package n overall configuration is 1m x 32 n +5v operation (standard) or +3.3v (consult factory) n access times of 80, 100 and 120 ns ( 5v v c c ) n +5v or +12v programing n erase/program cycles l 100,000 commercial l 10,000 military and industrial n sector architecture (each die) l one 16k protected boot block ( bottom boot block standard, top boot block special order ) l two 8k parameter blocks l one 96k main block l seven 128k main blocks n single block erase (all bits set to 1) n hardware data protection feature n independent boot block locking n mil-prf-38534 compliant mcms available n packaging ? hermetic ceramic l 68 lead, .94" x .94" x .180" dual-cavity small outline gull wing, aeroflex code# "f14" (drops into the 68 lead jedec .99"sq cqfj footprint) n internal decoupling capacitors for low noise operation n commercial, industrial and military temperature ranges circuit technology standard configuration pin description i/o 0-31 data i/o a 0?19 address inputs we write enables ce 1-4 chip enables oe output enable wp write protect rp reset/powerdown v cc power supply gnd ground nc not connected pin description i/o 0-31 data i/o a 0?19 address inputs we 1-4 write enable ce 1-4 chip enables oe output enable rp reset/powerdown v cc power supply gnd ground nc not connected 1mx8 1mx8 1mx8 1mx8 ce 4 oe a 0 ? a 19 i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 8 8 8 8 ce 3 we 4 we 3 we 2 we 1 ce 1 ce 2 rp 1mx8 1mx8 1mx8 1mx8 ce 4 oe a 0 ? a 19 i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 8 8 8 8 ce 3 we ce 1 ce 2 wp rp optional configuration www.aeroflex.com/act1.htm boot block flash multichip module act?f1m32 high speed 32 megabit
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 2 accomplished by chip enable ( ce ) and output enable ( oe ) being logically active. access time grades of 80ns, 100ns and 120ns maximum are standard. the act?f1m32 is packaged in a hermetically sealed co-fired ceramic 68 lead, .94" sq ceramic gull wing cqfp package. this allows operation in a military environment temperature range of -55c to +125c. the act?f1m32 provides program and erase capability at 5v or 12v and allows reads with vcc at 5v or 3.3v(not tested). since many designs read from flash memory a large percentage of the time, read operation using 3.3v can provide great power savings. consult the factory for 3.3v tested parts. in applications where read performance is critical, faster access times are obtainable with the 5v v c c part detailed herein. for program and erase operations, 5v vpp operation eliminates the need for in system voltage converters. the 12v vpp operation provides reduced (approx 60%) program and erase times where 12v is available in the system. for design simplicity, however, connect vcc and vpp to the same 5v 10% source. each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. the boot block is located at either the bottom (standard) or the top (special order) of the address map in order to accommodate different microprocessor protocols for boot code location. locking and unlocking of the boot block is controlled by wp and/or rp . intel's boot block architecture provides a flexible solution for the different design needs of various applications. the asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. the boot block provides a secure boot prom; the parameter blocks can emulate eeprom functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing ram requirements. for detail information regarding the operation of the 28f800bv memory die, see the intel datasheet (order number 290539-002). general description, cont?d , smartdie? is a trademark of intel corporation
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 3 absolute maximum ratings parameter range units case operating temperature range -55 to +125 c storage temperature range -65 to +150 c voltage on any pin with respect to gnd (except v c c , v p p , a 9 and rp ) (1) -2.0 to +7.0 v voltage on pins a 9 or rp with respect to gnd (except v c c , v p p , a 9 and rp ) (1,2) -2.0 to +13.5 v v p p program voltage with respect to gnd during block erase/ and word/byte write (1,2) -2.0 to +14.0 v vcc supply voltage with respect to ground (1) -2.0 to +7.0 v output short circuit current (3) 100 ma notes: 1. minimum dc voltage is -0.5v on input/output pins. during transitions, inputs may undershoot to -2.0v for periods < 20ns. max imum dc voltage on input/output pins is vcc + 0.5v, which may overshoot to vcc + 2.0v for periods < 20ns. 2. maximum dc voltage on vpp may overshoot to +14.0v for periods < 20ns. maximum dc voltage on rp or a 9 may overshoot to v c c + 0.5v for periods <20ns 3. output shorted for no more than 1 second. no more than one output shorted at one time. notice: stresses above those listed under "absolute maximums rating" may cause permanent damage. these are stress rating only. o peration beyond the "oper- ation conditions" is not recommended and extended exposure beyond the "operation conditions" may effect device reliability. recommended operating conditions symbol parameter minimum maximum units v c c 5v power supply voltage (10%) +4.5 +5.5 v 3.3v power supply voltage (0.3v) (consult factory) +3.0 +3.6 v v i h input high voltage (3.3v & 5v v c c ) +2.0 v cc + 0.5 v v i l input low voltage (3.3v & 5v v c c ) -0.5 +0.8 v t a operating temperature (military) -55 +125 c capacitance (f = 1mhz, t a = 25 c) symbol parameter maximum units c a d a 0 ? a19 capacitance 50 pf c o e oe capacitance 50 pf c c e ce capacitance 20 pf c r p rp capacitance 50 pf c w e we capacitance 60 pf c w p wp capacitance 50 pf c i / o i/o 0 ? i/o 31 capacitance 20 pf capacitance guaranteed by design, but not tested. dc characteristics ? cmos compatible (t a = -55 c to +125 c, v c c = +4.5v to + 5.5v(5v operation), or +3.0v to +3.6v(3.3v operation), unless otherwise specified) parameter sym conditions +3.3v v c c (1) typical +5.0v v c c standard units min max min max input load current i i l v c c = v c c max., v i n = v c c or gnd -1 +1 -1 +1 m a output leakage current i l o v c c = v c c max., v i n = v c c or gnd -10 +10 -10 +10 m a vcc standby current i c c s v c c = v c c max., ce = rp = wp = v c c 0.2v 440 600 m a vcc deep power-down current i c c d v c c = v c c max., v i n = v c c or gnd , rp = gnd 0.2v 32 32 m a vcc read current i c c r v c c = v c c max., ce = gnd , f = 10 mhz (5v), 5 mhz (3.3v), i o u t = 0 ma , inputs = gnd 0.2v or v c c 0.2v 120 260 ma vcc write current i c c w 1 v p p = v p p h 1 ( at 5v) , word write in progress (x32) 120 200 ma i c c w 2 v p p = v p p h 2 ( at 12v) , word write in progress (x32) 100 180 ma vcc erase current i c c e 1 v p p = v p p h 1 ( at 5v) ,block erase in progress 120 180 ma i c c e 2 v p p = v p p h 2 ( at 12v) ,block erase in progress 100 160 ma vcc erase suspend current i c c e s ce = v i h , block erase suspend 32 48 ma v p p standby current i p p s v p p < v p p h 2 60 60 m a
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 4 v p p deep power down current i p p d rp = gnd 0.2v 40 40 m a v p p read current i p p r v p p > v p p h 2 800 800 m a v p p write current i p p w 1 v p p = v p p h 1 ( at 5v) , word write in progress (x32) 120 120 ma i p p w 2 v p p = v p p h 2 ( at 12v) , word write in progress (x32) 100 100 ma v p p erase current i p p e 1 v p p = v p p h 1 ( at 5v) , block erase in progress 120 100 ma i p p e 2 v p p = v p p h 2 ( at 12v) , block erase in progress 100 80 ma v p p erase suspend current i p p e s v p p = v p p h , block erase suspend in progress 800 800 m a rp boot block unlock current i r p rp = v h h , v p p = 12v 2 2 ma output low voltage v o l v c c = v c c min., i o l = 5.8 ma (5v), 2 ma (3.3v) 0.45 0.45 v output high voltage v o h 1 v c c = v c c min., i o h = -2.5 ma 0.85 x v c c 0.85 x v c c v v o h 2 v c c = v c c min., i o h = -100 a v c c - 0.4v v c c - 0.4v v v p p lock-out voltage v p p l k complete write protection 0.0 1.5 0.0 1.5 v v p p (program/erase operations) v p p h 1 v p p = at 5v 4.5 5.5 4.5 5.5 v v p p (program/erase operations) v p p h 2 v p p = at 12v 11.4 12.6 11.4 12.6 v v c c erase/write lock voltage v l k o locked condition 0 2.0 0 2.0 v rp unlock voltage v h h boot block write/erase, v p p = 12v 11.4 12.6 11.4 12.6 v notes: 1. performance at v c c = +4.5v to +5.5v is guaranteed. performance at v c c = +3.3v is typical (not tested). ac characteristics ? write/erase/program operations ? we controlled (t a = -55 c to +125 c, v c c = +4.5v to + 5.5v(5v operation), or +3.0v to +3.6v(3.3v operation), unless otherwise specified) parameter symbol jedec standard +3.3v v c c (2) typical +4.5v to +5.5v v c c units 120ns min max 80ns min max 100ns min max 120ns min max write cycle time t a v a v 120 80 100 120 ns rp high recovery to we going low t p h w l 1.5 .45 .45 .45 m s ce setup to we going low t e l w l 0 0 0 0 ns boot block unlock setup to we going high (1) t p h h w h 200 100 100 100 ns v p p setup to we going high (1) t v p w h 200 100 100 100 ns address setup to we going high t a v w h 90 60 60 60 ns data setup to we going high t d v w h 70 60 60 60 ns we pulse width t w l w h 90 60 60 60 ns data hold time from we high t w h d x 0 0 0 0 ns address hold time from we high t w h a x 0 0 0 0 ns ce hold time from we high t w h e h 0 0 0 0 ns we pulse width high t w h w l 30 20 20 20 ns duration of word write operation (1) (x32) t w h q v 1 6 6 6 6 m s duration of erase operation (boot) (1) t w h q v 2 0.3 0.3 0.3 0.3 sec duration of erase operation (parameter) (1) t w h q v 3 0.3 0.3 0.3 0.3 sec duration of erase operation (main) (1) t w h q v 4 0.6 0.6 0.6 0.6 sec v p p hold from valid srd (1) t q v v l 0 0 0 0 ns rp v h h hold from valid srd (1) t q v p h 0 0 0 0 ns boot block lock delay (1) t p h b r 200 100 100 100 ns notes: 1. guaranteed by design, not tested. 2. performance at v c c = +4.5v to +5.5v is guaranteed. performance at v c c = +3.3v is typical (not tested). dc characteristics ? cmos compatible (t a = -55 c to +125 c, v c c = +4.5v to + 5.5v(5v operation), or +3.0v to +3.6v(3.3v operation), unless otherwise specified) parameter sym conditions +3.3v v c c (1) typical +5.0v v c c standard units min max min max
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 5 ac characteristics ? write/erase/program operations, ce controlled (t a = -55 c to +125 c, v c c = +4.5v to + 5.5v(5v operation), or +3.0v to +3.6v(3.3v operation), unless otherwise specified) parameter symbol jedec standard +3.3v v c c (2) typical +4.5v to +5.5v v c c units 120ns min max 80ns min max 100ns min max 120ns min max write cycle time t a v a v 120 80 100 120 ns rp high recovery to ce low t p h e l 1.5 .45 .45 .45 m s we setup to ce going low t w l e l 0 0 0 0 ns boot block unlock setup to ce going high (1) t p h h e h 200 100 100 100 ns v p p setup to ce going high (1) t v p e h 200 100 100 100 ns address setup to ce going high t a v e h 90 60 60 60 ns data setup to ce going high t d v e h 70 60 60 60 ns ce pulse width t e l e h 90 60 60 60 ns data hold time from ce high t e h d x 0 0 0 0 ns address hold time from ce high t e h a x 0 0 0 0 ns we hold time from ce high t e h w h 0 0 0 0 ns ce pulse width high t e h e l 20 20 20 20 ns duration of word write operation (1) (x32) t e h q v 1 6 6 6 6 m s duration of erase operation (boot) (1) t e h q v 2 0.3 0.3 0.3 0.3 sec duration of erase operation (parameter) (1) t e h q v 3 0.3 0.3 0.3 0.3 sec duration of erase operation (main) (1) t e h q v 4 0.6 0.6 0.6 0.6 sec v p p hold from valid srd (1) t q v v l 0 0 0 0 ns rp v h h hold from valid srd (1) t q v p h 0 0 0 0 ns boot block lock delay (1) t p h b r 200 100 100 100 ns notes: 1. sampled, but not 100% tested. 2. performance at v c c = +4.5v to +5.5v is guaranteed. performance at v c c = +3.3v is typical (not tested). ac characteristics ? read only operations (t a = -55 c to +125 c, v c c = +4.5v to + 5.5v(5v operation), or +3.0v to +3.6v(3.3v operation), unless otherwise specified) parameter symbol jedec standard +3.3v v c c (2) typical +4.5v to +5.5v v c c units 120ns min max 80ns min max 100ns min max 120ns min max read cycle time t a v a v 120 80 100 120 ns address to output delay t a v q v 120 80 100 120 ns ce to output delay t e l q v 120 80 100 120 ns rp to output delay t p h q v 1.5 .45 .45 .45 m s oe to output delay t g l q v 65 40 40 40 ns ce to output in low z (1) t e l q x 0 0 0 0 ns ce to output in high z (1) t e h q z 55 30 30 30 ns oe to output in low z (1) t g l q x 0 0 0 0 ns oe to output in high z (1) t g h q z 45 30 30 30 ns output hold from address, ce, or oe change, whichever occurs first (1) t o h 0 0 0 0 ns notes: 1. guaranteed by design, but not tested. 2. performance at v c c = +4.5v to +5.5v is guaranteed. performance at v c c = +3.3v is typical (not tested).
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 6 ac waveforms for write and erase operations, we controlled a i n a i n addresses oe ce data we v p p rp d i n valid srd d i n d i n v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v p p l k v i l v p p h 2 v p p h 1 t a v a v t a v w h t w h a x t e l w l t w h e h t w h w l t w l w h t w h d x t d v w h t v p w h t w h q v 1,2,3,4 t p h w l high z ac test circuit v i h v i l wp 6.5v v h h t p h h w h t q v p h t q v v l write program or erase setup command power-up standby valid address & data (program) or erase confirm command automated program or erase delay read status register data write read array command v c c write device under test c l r 2 r 1 v c c test configuration component values test configuration c l (pf) r1 ( w ) r2 (w ) 3.3v standard test 50 990 770 5v standard test 50 580 390 notes: c l includes jig capacitance. o u t parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference level 1.5 v
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 7 ac waveforms for write and erase operations, ce controlled a i n a i n addresses oe we data ce v p p rp d i n valid srd d i n d i n v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v p p l k v i l v p p h 2 v p p h 1 t a v a v t a v e h t e h a x t w l e l t e h w h t e h e l t e l e h t e h d x t d v e h t v p e h t e h q v 1,2,3,4 t p h e l high z v i h v i l wp 6.5v v h h t p h h e h t q v p h t q v v l write program or erase setup command power-up standby valid address & data (program) or erase confirm command automated program or erase delay read status register data write read array command v c c write ac waveform for read operations addresses oe ce data we rp v i h v i l v i h v i l v i h v i l v i h v i l v o h v o l v i h v i l standby device and address selection outputs enabled data valid standby addresses stable valid output t p h q v t a v q v t e l q x t g l q x t e l q v t g l q v t o h t g h q z t e h q z t a v a v high z high z v i h v i l
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 8 pin numbers & functions 68 pins ? dual-cavity cqfp (standard configuration) pin # function pin # function pin # function pin # function 1 gnd 18 gnd 35 oe 52 gnd 2 ce 3 19 i/o 8 36 ce 2 53 i/o 23 3 a 5 20 i/o 9 37 a 17 54 i/o 22 4 a 4 21 i/o 10 38 wp 55 i/o 21 5 a 3 22 i/o 11 39 nc 56 i/o 20 6 a 2 23 i/o 12 40 nc 57 i/o 19 7 a 1 24 i/o 13 41 a 18 58 i/o 18 8 a 0 25 i/o 14 42 a 19 59 i/o 17 9 rp 26 i/o 15 43 v p p 60 i/o 16 10 i/o 0 27 v c c 44 i/o 31 61 v c c 11 i/o 1 28 a 11 45 i/o 30 62 a 10 12 i/o 2 29 a 12 46 i/o 29 63 a 9 13 i/o 3 30 a 13 47 i/o 28 64 a 8 14 i/o 4 31 a 14 48 i/o 27 65 a 7 15 i/o 5 32 a 15 49 i/o 26 66 a 6 16 i/o 6 33 a 16 50 i/o 25 67 we 17 i/o 7 34 ce 1 51 i/o 24 68 ce 4 consult factory for special order (optional configuration) : pin 38 - we 2 , pin 39 - we 3, pin 40 - we 4 and pin 67 - we 1 "f14" ? cqfp dual-cavity flat package all dimensions in inches 0.015 0.990 sq .010 0.940 sq .010 0.800 ref see detail ?a? .002 pin 60 pin 44 pin 43 pin 27 pin 26 pin 10 pin 9 0.750 max pin 61 0.180 0.01r detail ?a? .008 +.002 .040 .010 .008 -.001
aeroflex circuit technology scd1661b rev a 1/16/97 plainview ny (516) 694-6700 9 ordering information model number screening speed package act?f1m32b?080f14c commercial (0c to +70c) 80 ns cqfp act?f1m32b?100f14c commercial (0c to +70c) 100 ns cqfp act?f1m32b?120f14c commercial (0c to +70c) 120 ns cqfp act?f1m32b?080f14i industrial (-40c to +85c) 80 ns cqfp act?f1m32b?100f14i industrial (-40c to +85c) 100 ns cqfp act?f1m32b?120f14i industrial (-40c to +85c) 120 ns cqfp act?f1m32b?080f14m military (-55c to +125c) 80 ns cqfp act?f1m32b?100f14m military (-55c to +125c) 100 ns cqfp act?f1m32b?120f14m military (-55c to +125c) 120 ns cqfp act?f1m32b?080f14q desc drawing pending mil-prf-38534 compliant 80 ns cqfp act?f1m32b?100f14q desc drawing pending mil-prf-38534 compliant 100 ns cqfp act?f1m32b?120f14q desc drawing pending mil-prf-38534 compliant 120 ns cqfp circuit technology part number breakdown act? f 1m 32 b? 080 f14 m aeroflex circuit technology memory type s = sram f = flash eeprom e = eeprom d = dynamic ram memory depth, locations pinout options memory width, bits b = bottom boot block (standard), t= top boot block (special order) memory speed, ns (+5v v c c ) package type & size surface mount packages f14 = .94" sq 68 lead\dual-cavity cqfp c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * q = mil-prf-38534 compliant/smd if applicable screening * screened to the individual test methods of mil-std-883 aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: (800) 843-1553 specifications subject to change without notice www.aeroflex.com/act1.htm e-mail: sales-act@aeroflex.com
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